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| datasheet AX8052F100 ultra - low power microcontroller revision 2
www.onsemi.com AX8052F100 2 table of contents 1. overview .................................................................................................................. 4 1.1. features .................................................................................................................... 4 1.2. applications ............................................................................................................... 6 2. block diagram .......................................................................................................... 7 3. pin function descriptions ......................................................................................... 8 3.1. alternate pin functions ................................................................................................ 9 3.2. pinout drawing .......................................................................................................... 10 4. specifications ......................................................................................................... 11 4.1. absolute maximum ratings ......................................................................................... 11 4.2. dc characteristics ..................................................................................................... 12 supplies .................................................................................................................... 12 logic ........................................................................................................................ 13 4.3. ac characteristics ...................................................................................................... 13 crystal oscillator ........................................................................................................ 13 low frequency crystal oscillator .................................................................................. 14 internal low power oscillator ...................................................................................... 14 internal rc oscillator .................................................................................................. 14 microcontroller ........................................................................................................... 15 adc / comparator / temperature sensor ...................................................................... 16 5. circuit description .................................................................................................. 17 5.1. microcontroller .......................................................................................................... 18 memory architecture .................................................................................................. 18 memory map .............................................................................................................. 19 power management .................................................................................................... 21 clocking .................................................................................................................... 21 reset and interrupts .................................................................................................. 22 debugging ................................................................................................................ 23 5.2. timer, output compare and input capture ................................................................... 24 table of contents www.onsemi.com AX8052F100 3 5.3. uart ....................................................................................................................... 24 5.4. dedicated radio spi master controller .......................................................................... 24 5.5. spi master/slave controller ........................................................................................ 24 5.6. adc, analog comparators and temperature sensor ....................................................... 25 5.7. dma controller .......................................................................................................... 26 5.8. aes engine ............................................................................................................... 26 5.9. crystal oscillator ....................................................................................................... 26 5.10. ports ................................................................................................................... 27 6. application information ......................................................................................... 28 6.1. typical application diagram ........................................................................................ 28 7. qfn28 package information .................................................................................. 29 7.1. package outline qfn28 .............................................................................................. 29 7.2. qfn28 soldering profile .............................................................................................. 30 7.3. qfn28 recommended pad layout ................................................................................ 31 7.4. assembly process ...................................................................................................... 31 stencil design & solder paste application ...................................................................... 31 8. references ............................................................................................................. 33 9. device versions ...................................................................................................... 34 overview www.onsemi.com AX8052F100 4 1. overview 1.1. feature s ultra - low power microcontroller ? qfn28 package ? supply range 1.8 v - 3.6 v ? - 40c to 85c ? ultra - low power consumption: o cpu active mode 150 a/mhz o sleep mode with 256 byte ram retention and wake - up timer running 850 n a o sleep mode 4 kbyte ram retention and wake - up timer running 1.5 a o sleep mode 8 kbyte ram retention and wake - up timer running 2.2 a ? ax8052 core o industry standard 8052 instructio n set o high performance core, most instructions require only 1 clock per instruction byte o 20 mips o dual dptr for high speed memory copies o 22 interrupt vectors ? debugger o 3 - wire (1 dedicated, 2 shared with gpio pins) debugger interface o true hardware debugger wi th breakpoints and single stepping support o user programmable 64bit key to restrict debugging to authorized personnel o debuglink interface allows "printf" style debugging without utilizing a uart or gpio pins ? memory o 64 kbyte flash 100 000 erase cycles 10 yea r data retention o 8.25 kbyte ram o high performance memory crossbar ? clocking o 4 clock sources ? on - chip 20 mhz rc - oscillator ? 10 khz/640 hz ultra - lowpower rc - oscillator ? fast crystal oscillator ? low power tuning fork crystal oscillator o fully automatic calibration of on - chip rc oscillators to a reference clock o clock monitor can detect failures of the main clock and switch to the on - chip fast rc oscillator o watchdog ? power modes o standby, sleep and deep sleep power modes for very low idle power consumption o on - chip powe r - on reset and brown out detection o unrestricted operation from 1.8 v - 3.6 v vdd_io overview www.onsemi.com AX8052F100 5 ? 16- bit wakeup timer o 2 counting registers o 4 event registers allow flexible wakeup and software schedules ? gpio o 24 gpio pins o pb0 - pb7, pc0- pc3 and pr0 - pr5 5 v tolerant inputs o a ll gpio pins support individually programmable pull - ups and interrupt on change o flexible allocation of gpio pins to peripherals ? 16- bit general purpose timer (3x) o saw tooth and triangle modes o sigma - delta mode converts timer into a dac o optional double buffe ring of the period register allows controlled frequency changes o optional high - byte buffering allows atomic 16 - bit accesses o flexible clocking options, can use any internal or an external clock source o pre - scaler included ? 16- bit output compare unit (2x) o used together with a general purpose timer to create pwm waveforms o optional double buffering ? 16- bit input capture unit (2x) o used together with a general purpose timer to time events on an external or internal signal ? uart (2x) o 5 - 9 bit word length, 1 - 2 stop bits o uses one of the general purpose timers as baud rate generator ? dedicated radio master spi interface o compatible to axsem rf and other peripherals o efficient cpu access o easy access to transceiver registers by mapping transceiver registers into x address space o transceiver crystal may clock mcu ? master/slave spi o supports 3 and 4 wire variants ? adc o 10- bit 500 ksamples/s adc o up to 8 channels o single ended and differential sampling o x0.1, x1 and x10 gain amplifier o internal 1 v reference o flexibly programmable conversio n schedule o built - in temperature sensor ? analog comparators o internal or external reference o output signal may be routed to gpio, read by software, or used as input capture trigger overview www.onsemi.com AX8052F100 6 ? dma controller o 2 independent dma channels o moves data between x - ram and most on - chip peripherals o cycle - steal and round- robin memory arbitration ensure minimal impact on ax8052 core o chained buffer descriptors allow arbitrarily elaborate buffering schemes and flexible interrupt generation ? aes 1 o dedicated aes crypto controller o dedicated dma engine to fetch input data and key stream from x - ram and strobe output data into x - ram o multi megabit/s data rates o supports aes - 128, aes - 192 and aes - 256 international standards o programmable round number and software key schedule generation allow longer key lengths for higher security applications o ecb, cfb and ofb chaining modes ? true random number generator (rng) 1 o cryptographic random numbers 1.2. applications ? ultra - low power microcontroller applications, especially in conjunction with axsem radio ic ? senso r applications ? home automation ? automatic meter reading ? remote keyless entry ? active rfid ? wireless audio 1 the aes engine and the random number generator require software enabling and support. block diagram www.onsemi.com AX8052F100 7 2. block diagram 256 debug interface axsem 8052 system controller flash 64k aes crypto engine adc comparators spi m/s uart 1 uart 0 input capt 1 input capt 0 output comp 1 output comp 0 timer counter 2 timer counter 1 timer counter 0 gpio pa0 pa1 pa2 pa3 pa4 pa5 reset_n gnd vdd_io 8k ram pc0 pc1 pc2 pc3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 i/o multiplexer dbg_en irq req reset, clocks, power i-bus p-bus x-bus sfr-bus dma controller dma req temp sensor por pr0 pr1 pr2 pr3 pr4 pr5 AX8052F100 figure 1 functional block diagram of the AX8052F100 pin function descriptions www.onsemi.com AX8052F100 8 3. pin function descriptions symbol pin(s) type description pr5 1 i/o/pu general purpose i/o vdd_core 2 p regulated output voltage pr4 3 i/o/pu general pur pose i/o pr3 4 i/o/pu general purpose i/o pr2 5 i/o/pu general purpose i/o pr1 6 i/o/pu general purpose i/o pr0 7 i/o/pu general purpose i/o pc3 8 i/o/pu general purpose i/o pc2 9 i/o/pu general purpose i/o pc1 10 i/o/pu general purpose i/o pc0 11 i/o/pu general purpose i/o pb0 12 i/o/pu general purpose i/o pb1 13 i/o/pu general purpose i/o pb2 14 i/o/pu general purpose i/o pb3 15 i/o/pu general purpose i/o pb4 16 i/o/pu general purpose i/o pb5 17 i/o/pu general purpose i/o pb6, dbg_data 18 i/o/pu general purpose i/o, debugger data line pb7, dbg_clk 19 i/o/pu general purpose i/o, debugger clock line dbg_en 20 i/pd in - circuit debugger enable reset_n 21 i/pu optional reset pin. if this pin is not used it must be connected to vdd_io vdd_io 2 2 p unregulated power supply pa0 23 i/o/pu general purpose i/o pa1 24 i/o/pu general purpose i/o pa2 25 i/o/pu general purpose i/o pa3 26 i/o/pu general purpose i/o pa4 27 i/o/pu general purpose i/o pa5 28 i/o/pu general purpose i/o gnd center pad p ground on center pad of qfn, must be connected a = analog signal i/o = digital input/output signal i = digital input signal n = not to be connected o = digital output signal p = power or ground pu = pull - up pd = pull - down all digital inputs are schmitt trigger inputs, digital input and output levels are lvcmos/lvttl compatible. port a pins (pa0 - pa7) must not be driven above vdd_io, all other digital inputs are 5v tolerant. pull - ups are programmable for all gpio pins. pin function descriptions www.onsemi.com AX8052F100 9 3.1. alternate pin function s gpio pins are shared with dedicated input/output signals of on - chip peripherals. the following table lists the available functions on each gpio pin. gpio alternate functions pa0 t0out ic1 adc0 xtalp pa1 t0clk oc1 adc1 xtaln pa2 oc0 u1rx adc2 compi00 pa3 t1out adc3 lpxtalp pa4 t1clk compo0 adc4 lpxtaln pa5 ic0 u1tx adc5 compi10 pb0 u1tx ic1 extirq0 pb1 u1rx oc1 pb2 ic0 t2out pb3 oc0 t2clk extirq1 dswake pb4 u0tx t1clk pb5 u0rx t1out pb6 dbg_data pb7 dbg_clk pc0 ssel t0out ext irq0 pc1 ssck t0clk compo1 pc2 smosi u0tx pc3 smiso u0rx compo0 pr0 rsel pr1 rsysclk pr2 rclk pr3 rmiso pr4 rmosi pr5 rirq pin function descriptions www.onsemi.com AX8052F100 10 3.2. pinout drawing figure 2 pin - out drawing (top view) pa5/adc5/ic0/u1tx/compi10 22 23 25 24 26 27 28 14 13 11 12 10 9 8 7 1 2 3 4 5 6 15 21 20 19 18 17 16 rirq/pr5 rsel/pr0 vdd_core rmiso/pr3 rclk/pr2 rmosi/ pr4 rsysclk/pr1 reset_n pb4/u0tx/t1clk dbg_en pb6/dbg_data pb5/u0rx/t1out pb7/dbg_clk pb3/oc0/t2clk/extirq1/dswake compo0/u0rx/smiso/pc3 u0tx/smosi/pc2 compo1/t0clk/ssck/pc1 extirq0/ t0out/ssel/pc0 extirq0/ic1/u1tx/pb0 oc1/u1rx/pb1 t2out/ic0/pb2 pa4/adc4/t1clk/compo0/lpxtaln pa3/adc3/t1out/lpxtalp pa0/adc0/t0out/ic1/xtaln pa2/adc2/oc0/u1rx/compi00 pa1/adc1/t0 clk/oc1/xtalp vdd_io AX8052F100 spe cifications www.onsemi.com AX8052F100 11 4. specifications 4.1. absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol description condition min max u nit vdd_io supply voltage - 0.5 5.5 v idd supply current 100 ma p tot total power consumption 800 mw i i1 dc current into any pin - 10 10 ma i i2 dc current into pins - 100 100 ma i o output current 40 ma v ia input voltage digital pins - 0.5 5.5 v v es electrostatic handling hbm - 2000 2000 v t amb operating temperature - 40 85 c t stg storage temperature - 65 150 c t j junction temperature 150 c specifications www.onsemi.com AX8052F100 12 4.2. dc characteristics supplies symbol description condition min typ max unit t amb operational amb ient temperature - 40 27 85 c vdd_io i/o and voltage regulator supply voltage 1.8 3.0 3.6 v vdd io_r1 i/o voltage ramp for reset activation; note 1 ramp starts at vdd_io0.1v 0.1 v/ms vdd io_r2 i/o voltage ramp for reset activation; note 1 ramp starts at 0.1v specifications www.onsemi.com AX8052F100 14 low frequency crystal oscillator symbol description condition min typ max unit f lpxtal crystal frequency 32 150 khz gm lpxosc transconductance oscillator lpxoscgm=00110 3.5 s lpxoscgm=01 000 4.6 lpxoscgm=01100 6.9 lpxoscgm=10000 9.1 rin lpxosc input dc impedance 10 m ? internal low power oscillator symbol description condition min typ max unit f lposc oscillation frequency lposcfast=0 factory calibration applied. over th e full temperature and voltage range 630 640 650 hz lposcfast=1 factory calibration applied. over the full temperature and voltage range 10.08 10.24 10.39 khz internal rc oscillator symbol description condition min typ max unit f frcosc oscillation fr equency factory calibration applied. over the full temperature and voltage range 19.8 20 20.2 mhz specifications www.onsemi.com AX8052F100 15 microcontroller symbol description condition min typ max unit t sysclkl sysclk low 27 ns t sysclkh sysclk high 21 ns t sysclkp sysclk period 47 n s t flwr flash write time 2 bytes 20 s t flpe flash page erase 1 kbytes 2 ms t fle flash secure erase 64 kbytes 10 ms t flend flash endurance: erase cycles 10 000 100 000 cycles t flretroom flash data retention 25 o c see fi gure 3 for the lower limit set by the memory qualification 100 years t flrethot 85 o c see figure 3 for the lower limit set by the memory qualification 10 10 100 1000 10000 100000 15 25 35 45 55 65 75 85 temperature [ o c] data retention time [years] figure 3 flash memory qualification limit for data retention after 10k erase cycles specifications www.onsemi.com AX8052F100 16 adc / comparator / temperature sensor symbol description condition min typ max unit adcsr adc sampling rate gpadc mode 30 500 khz adcsr_t adc sampling rate temperature sensor mode 1 0 15.6 30 khz adcres adc resolution 10 bits v adcref adc reference voltage & comparator internal reference voltage 0.95 1 1.05 v z adc00 input capacitance 2.5 pf dnl differential nonlinearity +/ - 1 lsb inl integral nonlinearity +/ - 1 lsb o ff offset 3 lsb gain_err gain error 0.8 % adc in differential mode v abs_diff absolute voltages & common mode voltage in differential mode at each input 0 vdd_io v v fs_diff01 full swing input for differential signals gain x1 - 500 500 mv v fs_di ff10 gain x10 - 50 50 mv adc in single ended mode v mid_se mid code input voltage in single ended mode 0.5 v v in_se00 input voltage in single ended mode 0 vdd_io v v fs_se01 full swing input for single ended signals gain x1 0 1 v v fs_se10 gain x 10 0.45 0.55 v comparators v comp_abs comparator absolute input voltage 0 vdd_io v v comp_com comparator input common mode 0 vdd_io - 0.8 v v compoff comparator input offset voltage 20 mv temperature sensor t rng temperature range - 40 85 c t res temperature resolution 0.1607 c/lsb t err_cal temperature error factory calibration applied - 2 +2 c circuit description www.onsemi.com AX8052F100 17 5. circuit description the AX8052F100 is a single chip ultra - lowpower microcontroller primarily for use in radio applications. the AX8052F100 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. it contains 64 kbytes of flash and 8.25 kbytes of internal sram. the AX8052F100 features 3 16 - bit general purpose timers with ? capability, 2 output compare units for generating pwm signals, 2 input compare units to record timings of external signals, 2 16- bit wakeup timers, a watchdog timer, 2 uarts, a ma ster/slave spi controller, a 10 - bit 500 ksample/s a/d converter, 2 analog comparators, a temperature sensor, a 2 channel dma controller, and a dedicated aes crypto controller. debugging is aided by a dedicated hardware debug interface controller that con nects using a 3 - wire protocol (1 dedicated wire, 2 shared with gpio) to the pc hosting the debug software. the system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from one of the following clock sources: the crystal oscillator, an internal high speed 20 mhz oscillator, an internal low speed 640 hz/10 khz oscillator, or the low frequency crystal oscillator. pre - scalers offer additional flexibility with their programmable divide by a power of two capability. to improve the accuracy of the internal oscillators, both oscillators may be slaved to the crystal oscillator. AX8052F100 can be operated from a 1.8 v to 3.6 v power supply over a temperature range of - 40 o c to 85 o c. the AX8052F100 features make it an ideal interface for integration into various battery powered srd solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. circuit description www.onsemi.com AX8052F100 18 5.1. microcontroller the AX8052F100 microcontroller core executes the industry standard 8052 instruction set. unlike the original 8052, many instructions are executed in a single cycle. the system clock and thus the instruction rate can be programmed freely from dc to 20 mhz. memory architecture arbiter xram 0000-0fff arbiter xram 1000-1fff arbiter x registers 4000-7fff arbiter sfr registers 80-ff arbiter iram 00-ff arbiter flash 0000-ffff aes dma x bus ax8052 sfr bus iram bus code bus cache prefetch figure 4 ax8052 memory architecture the ax8052 microcontroller features the highest bandwidth memory architecture of its class. figure 4 shows the memory architecture. three bus masters may initiate bus cycles: ? the ax8052 microcontroller core ? the direct memory access (dma) engine ? the advanced encryption standard (aes) engine bus targets include: ? two individual 4 kbytes ram blocks located i n x address space, which can be simultaneously accessed and individually shut down or retained during sleep mode ? a 256 byte ram located in internal address space, which is always retained during sleep mode ? a 64 kbytes flash memory located in code space. ? sp ecial function registers (sfr) located in internal address space accessible using direct address mode instructions ? additional registers located in x address space (x registers) circuit description www.onsemi.com AX8052F100 19 the upper half of the flash memory may also be accessed through the x address s pace. this simplifies and makes the software more efficient by reducing the need for generic pointers 1 . sfr registers are also accessible through x address space, enabling indirect access to sfr registers. this allows driver code for multiple identical per ipherals (such as uarts or timers) to be shared. the 4 word 16 bit fully associative cache and a pre - fetch controller hide the latency of the flash. the ax8052 memory architecture is fully parallel. all bus masters may simultaneously access different bus targets during each system clock cycle. each bus target includes an arbiter that resolves access conflicts. each arbiter ensures that no bus master can be starved. both 4 kbytes ram blocks may be individually retained or switched off during sleep mode. th e 256 byte ram is always retained during sleep mode. the aes engine accesses memory 16bits at a time. it is therefore slightly faster to align its buffers on even addresses. memory map xram flash 0000-007f 0080-00ff 0100-1fff 2000-207f 2080-3f7f 3f80-3fff 4000-4fff 5000-5fff 6000-7fff 8000-fbff fc00-ffff address calibration data iram iram p (code) space x space i (internal) space direct access indirect access sfr iram sfr rreg rreg (nb) xreg flash calibration data figure 5 ax8052 m emory map the ax8052, like the other industry standard 8052 compatible microcontrollers, uses a harvard architecture. multiple address spaces are used to access code and data. figure 5 shows the ax8052 memory map. 1 generic pointers include, in addition to the address, an address space tag. circuit description www.onsemi.com AX8052F100 20 the ax8052 uses p or code space to access its program. code space may also be read using the movc instruction. smaller amounts of data can be placed in the internal 2 or data space. a distinction is made in the upper half of the data space between direct accesses ( mov reg, addr ; mov addr,reg ) and indirect accesses ( mov reg,@ri ; mov @ri,reg ; push ; pop ); direct accesses are routed to the special function registers, while indirect accesses are routed to the internal ram. large amounts of data can be placed in the external or x space. it can be accessed using the movx instructions. special function registers, as well as additional microcontroller registers (xreg) and the radio registers (rreg) are also mapped into the x space. detailed documentation of the special function regist ers (sfr) and additional microcontroller registers can be found in the ax8052 programming manual. the radio registers are documented in the programming manual of the connected radio chip. register addresses given in the radio chip?s programming manual are relative to the beginning of rreg, i.e. 0x4000 must be added to these addresses. if an axsem radio chip is connected, the appropriate axsem provided ax8052f1xx.h header file should be used. normally, accessing radio registers through the rreg address range is adequate. since radio register accesses have a higher latency than other ax8052 registers, the ax8052 provides a method for non - blocking access to the radio registers. accessing the rreg (nb) address range initiates a radio register access, but does no t wait for its completion. the details of mechanism is documented in the radio interface section of the ax8052 programming manual. the flash memory is organized as 64 pages of 1 kbytes each. each page can be individually erased. the write word size is 16 b its. the last 1 kbyte page is dedicated to factory calibration data and should not be overwritten. 2 the origin of internal versus exte rnal (x) space is historical. external space used to be outside of the chip on the original 8052 microcontrollers. circuit description www.onsemi.com AX8052F100 21 power management the micro - controller supports the following power modes: pcon register name description 00 running the microcontroller and all peripherals are running. current consumption depends on the system clock frequency and the enabled peripherals and their clock frequency. 01 standby the microcontroller is stopped. all register and memory contents are retained. all peripherals continue to function no rmally. current consumption is determined by the enabled peripherals. standby is exited when any of the enabled interrupts become active. 10 sleep the micro - controller and its peripherals, except gpio and the system controller, are shut down. their regist er settings are lost. the internal ram is retained. the external ram is split into two 4 kbyte blocks. software can determine individually for both blocks whether contents of that block are to be retained or lost. sleep can be exited by any of the enabled gpio or system controller interrupts. for most applications this will be a gpio or wakeup timer interrupt. 11 deepsleep the micro - controller, all peripherals and the transceiver are shut down. only 4 bytes of scratch ram are retained. deepsleep can only b e exited by tying the pb3 pin low. clocking lposc calib frcosc calib wakeup timer wdt clock monitor prescaler 1,2,4,... frcosc xosc lpxosc lposc interrupt internal reset rsysclk glitch free clock switch system clock figure 6 clock system diagram circuit description www.onsemi.com AX8052F100 22 the system clock can be derived from any of the following clock sources: ? the crystal oscillator ? the low speed crystal oscillat or ? the internal high speed rc (20 mhz) oscillator ? the internal low power (640 hz/10 khz) oscillator an additional pre - scaler allows the selected oscillator to be divided by a power of two. after reset, the microcontroller starts with the internal high spee d rc oscillator selected and divided by two. i.e. at start - up, the micro - controller runs with 10 mhz 10%. clocks may be switched any time by writing to the clkcon register. in order to prevent clock glitches, the switching takes approximately 2(t 1 +t 2 ), where t 1 and t 2 are the periods of the old and the new clock. switching may take longer if the new oscillator first has to start up. internal oscillators start up instantaneously, but crystal oscillators may take a considerable amount of time to start the oscillation. clkstat can be read to determine the clock switching status. a programmable clock monitor resets the clkcon register when no system clock transitions are found during a programmable time interval, thus reverts to the internal rc oscillator. bo th internal oscillators can be slaved to one of the crystal oscillators to increase the accuracy of the oscillation frequency. while the reference oscillator runs, the internal oscillator is slaved to the reference frequency by a digital frequency locked l oop. when the reference oscillator is switched off, the internal oscillator continues to run unslaved with the last frequency setting. reset and interrupts after reset, the microcontroller starts executing at address 0x0000. all registers except scratch0 ? s cratch3 are set to default values. ram is either retained (sleep mode) or undefined. several events can lead to resetting the micro - controller core: ? por or hardware reset_n pin activated and released ? leaving sleep or deepsleep mode ? watchdog reset ? software reset the reset cause can be determined by reading the pcon register. after por or reset all registers are set to their default values. AX8052F100 has an integrated power - on - reset block which is edge sensitive to vdd_ io. for many common application cases no external reset circuitry is required. however, if vdd_io ramps cannot be guaranteed, an external reset circuit is recommended. for detailed recommendations and requirements see the ax8052 application note: power on reset. the reset_n pin contains a weak pull - up. however, it is strongly recommended to connect the reset_n pin to vdd_io if not used, for additional robustness. circuit description www.onsemi.com AX8052F100 23 the micro - controller supports 22 interrupt sources. each interrupt can be individually enabled and can be programmed to have one of two possible priorities. the interrupt vectors are located at 0x0003, 0x000b, ?, 0x00ab. debugging a hardware debug unit considerably eases debugging compared to other 8052 microcontrollers. it allows to reliably stop the micro - controller at breakpoints even if the stack is smashed. the debug unit communicates with the host pc running the debugger using a 3 wire interface. one wire is dedicated (dbg_en), while two wires are shared with gpio pins (pb6, pb7). when dbg_en is driven high, pb6 and pb7 convert to debug interface pins and the gpio functionality is no longer available. a pin emulation feature however allows bits pinb[7:6] to be set and portb[7:6] and dirb[7:6] to be read by the debugger software. this allows fo r example switches or leds connected to the pb6, pb7 pins to be emulated in the debugger software whenever the debugger is active. in order to protect the intellectual property of the firmware developer, the debug interface can be locked using a developer - selectable 64 - bit key. the debug interface is then disabled and can only be enabled with the knowledge of this 64 - bit key. therefore, unauthorized persons cannot read the firmware through the debug interface, but debugging is still possible for authorized persons. secure erase can be initiated without key knowledge; secure erase ensures that the main flash array is completely erased before erasing the key, reverting the chip into factory state. the debuglink peripheral looks like an uart to the microcontrol ler, and allows exchange of data between the micro - controller and the host pc without disrupting program execution. ci rcuit description www.onsemi.com AX8052F100 24 5.2. timer, output compare and input capture the AX8052F100 features three general purpose 16 - bit timers. each timer can be clocked by the system clock, any of the available oscillators, or a dedicated input pin. the timers also feature a programmable clock inversion, a programmable prescaler that can divide by powers of two, and an optional clock synchronisa tion logic that synchronises the clock to the system clock. all three counters are identical and feature four different counting modes, as well as a ? mode that can be used to output an analog value on a dedicated digital pin only employing a simple rc lo wpass filter. two output compare units work in conjunction with one of the timers to generate pwm signals. two input capture units work in conjunction with one of the timers to measure transitions on an input signal. for software timekeeping, two additiona l 16 bit wakeup timers with 4 16 - bit event registers are provided, generating an interrupt on match events. 5.3. uart the AX8052F100 features two universal asynchronous receiver transmitters. they use one of the timers as baud rate generator. word length can be programmed from 5 to 9 bits. 5.4. dedicated radio spi master controller the AX8052F100 features a dedicated radio master spi controller. it is compatible with axsem rf chips as wel l as some third party spi slave devices. it features efficient access by the cpu. rf ic registers are mapped into the cpu x address space. 5.5. spi master/slave controller the AX8052F100 features a master/slave spi contro ller. both 3 and 4 wire spi variants are supported. in master mode, any of the on - chip oscillators or the system clock may be selected as clock source. an additional pre - scaler with divide by two capability provides additional clocking flexibility. shift d irection, as well as clock phase and inversion, are programmable. circuit description www.onsemi.com AX8052F100 25 5.6. adc, analog comparators and temperature sensor temperature sensor adc core clock trigger gain ref vref 1v vddio pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ppp nnn frcosc lposc xosc lpxosc sysclk system clock one shot free running timer 0 timer 1 timer 2 pc4 adc result acomp1ref acomp1st/pa7/pc1 acomp1in acomp1inv acomp0in acomp0ref acomp0inv acomp0st/pa4/pc3 system clock adcconv adcclksrc 0.1, 1, 10 single ended 0.5v prescaler 1,2,4,8,... figure 7 adc block diagram the AX8052F100 feature s a 10 - bit, 500 ksample/s analog to digital converter. the adc supports both single ended and differential measurements. it uses an internal reference of 1 v. 1, 10 and 0.1 gain modes are provided. the adc may digitize signals on pa0?pa7, as well as vdd _io and an internal temperature sensor. the user can define four channels which are then converted sequentially and stored in four separate result registers. each channel configuration consists of the multiplexer and the gain setting. circuit description www.onsemi.com AX8052F100 26 the AX8052F100 contains an on - chip temperature sensor. built - in calibration logic allows the temperature sensor to be calibrated in c, f or any other user defined temperature scale. the AX8052F100 also features two analog comparators. each comparator can either compare two voltages on dedicated pa pins, or one voltage against the internal 1 v reference. the comparator output can be routed to a dedicated digital output pin or can be read by software. the comparators are clocked with the system clock. 5.7. dma controller the AX8052F100 features a dual channel dma engine. each dma channel can either transfer data from xram to almost any peripheral on chip, or from almo st any peripheral to xram. both channels may also be cross - linked for memory - memory transfers. the dma channels use buffer descriptors to find the buffers where data is to be retrieved or placed, thus enabling very flexible buffering strategies. the dma ch annels access xram in a cycle steal fashion. they access xram whenever xram is not used by the micro - controller. their priority is lower than the micro - controller, thus interfering very little with the micro - controller. additional logic prevents starvation of the dma controller. 5.8. aes engine the AX8052F100 contains a dedicated engine for the government mandated advanced encryption standard (aes). it features a dedicated dma engine and reads input data as well as key str eam data from the xram, and writes output data into a programmable buffer in the xram. the round number is programmable; the chip therefore supports aes - 128, aes - 192, and aes - 256, as well as higher security proprietary variants. key stream (key expansion) is performed in software, adding to the flexibility of the aes engine. ecb (electronic codebook), cfb (cipher feedback) and ofb (output feedback) modes are directly supported without software intervention. in conjunction with the true random number generat or a high degree of security can be achieved. 5.9. crystal oscillator the on - chip crystal oscillator allows the use of an inexpensive quartz crystal as timing reference. normally, the oscillator operates fully automatically. it is powered on whenever the syste m clock or any peripheral clock is programmed to be derived from the crystal clock. to hide crystal startup latencies, the oscillator may also be forced on using the oscforcerun register. the transconductance of the oscillator is automatically controlled t o ensure fast startup and low steady state current consumption. for lowest phase noise applications, transconductance may be programmed manually using the xtalosc register. circuit description www.onsemi.com AX8052F100 27 5.10. ports vddio portx.y dirx.y special function paltx.y pinx read clock pinx.y interrupt intchgx.y analogx.y 65 k ? figure 8 port pin schem atic figure 8 shows the gpio logic. the dir register bit determines whether the port pin acts as an output (1) or an input (0). if configured as an output, the palt register bit determines whether the port pin is connected to a pe ripheral output (1), or used as a gpio pin (0). in the latter case, the port register bit determines the port pin drive value. if configured as an input, the port register bit determines whether a pull - up resistor is enabled (1) or disabled (0). inputs hav e schmitt - trigger characteristic. port a inputs may be disabled by setting the analoga register bit; this prevents additional current consumption if the voltage level of the port pin is mid - way between logic low and logic high, when the pin is used as an a nalog input. port a, b and c pins may interrupt the microcontroller if their level changes. the intchg register bit enables the interrupt. the pin register bit reflects the value of the port pin. reading the pin register also resets the interrupt if interr upt on change is enabled. application information www.onsemi.com AX8052F100 28 6. application information 6.1. typical application diagram figure 9 typical application diagram figure 9 shows a typical application schematic. short jumper j p1 - 1 if it is desired to supply the target board from the debug adapter (50ma max). connect the bottom exposed pad of the AX8052F100 to ground. if the debugger is not running, pb6 and pb7 are not driven by the debug a dapter. if the debugger is running, the pb6 and pb7 values the software reads may be set using the pin emulation feature of the debugger. pb3 is driven by the debugger only to bring the AX8052F100 out of deep sleep. i t is high impedance otherwise. port pins pr0 ? pr5 may be used to connect an axsem radio chip, or as general purpose i/o. crystals are optional. crystal load capacitances should be chosen according to the crystal datasheet. qfn28 package information www.onsemi.com AX8052F100 29 7. qfn28 package information 7.1. package outline qfn28 dimension min typ max unit a 0.800 0.850 0.900 mm notes 1. jedec ref mo - 220 2. all dimensions are in millimetres 3. pin 1 is identified by chamfer on corner of exposed die pad. 4. package warp shall be 0.050 maximum 5. coplanarity applies to the expo sed pad as well as the terminal 6. awl yyww is the packaging lot code 7. v is the device version 8. rohs on AX8052F100 - v awl yyww qfn28 package information www.onsemi.com AX8052F100 30 7.2. qfn28 soldering profile profile feature pb - free process average ramp - up rate 3 c/sec max. preheat preheat temperature min t smin 150c temperature max t smax 200c time (t smin to t smax ) t s 60 ? 180 sec time 25c to peak temperature t 25 to peak 8 min max. reflow phase liquidus temperature t l 217c time over li quidus temperature t l 60 ? 150 sec peak temperature t p 260c time within 5c of actual peak temperature t p 20 ? 40 sec cooling phase ramp - down rate 6c/sec max. notes: all temperatures refer to the top side of the package, measured on the package body surface. time t p t l t smax t smin t 25 to peak t s t l 25c preheat reflow cooling t p temperature qfn28 package information www.onsemi.com AX8052F100 31 7.3. qfn28 recommended pad layout 1. pcb land and solder masking recommendations are shown in figure 10. a = clearance from pcb thermal pad to solder mask opening, 0.0635 mm minimum b = clearance from edge of pcb thermal pad to pcb land, 0.2 mm minimum c = clearance from pcb land edge to solder mask opening to be as tight as possible to ensure that some s older mask remains between pcb pads d = pcb land length = qfn solder pad length + 0.1mm e = pcb land width = qfn solder pad width + 0.1 mm figure 10 pcb land and solder mask recommendations 2. thermal vias should be used on the pcb thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. the number of vias depends on the package thermal requirements, a s determined by thermal simulation or actual testing. 3. increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. in general, adding more metal through the p c board under the ic will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 7.4. assembly process stencil design & solder paste application 1. stainless steel stencils are recommended for solder paste application. 2. a stencil thickness of 0.125 ? 0.150 mm (5 ? 6 mils) is recommended for screening. 3. for the pcb thermal pad, solder paste should be printed on the pcb by designing a stencil with an array of smaller openings that sum to 50% of the qfn e xposed pad area. solder paste should be applied through an array of squares (or circles) as shown in figure 11. 4. the aperture opening for the signal pads should be between 50 - 80% of the qfn pad area as shown in figure 12. 5. optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 6. the fine pitch of the ic leads requires accurate alignment of the stencil and the printed circuit board. th e stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 7. no - clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water - soluble flux is used. qfn28 package information www.onsemi.com AX8052F100 32 figur e 11 solder paste application on exposed pad minimum 50% coverage 62% coverage maximum 80% coverage figure 12 solder paste application on pins references www.onsemi.com AX8052F100 33 8. references [1] on semiconductor ax8052 programming manu al, see http://www.onsemi.com [2] on semiconductor ax8052 silicon errata, see http://www.onsemi.com device versions www.onsemi.com AX8052F100 34 9. device versions the revision of the ax8052 silicon can be determined by the device marking or by reading the siliconrev register. [2] documents the differe nces between silicon revisions. device marking ax8052 version siliconrev AX8052F100 - 1 1 0x8e (10001110) AX8052F100 - 2 1c 0x8f (10001111) |
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